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Single-chip Type with Built-in FET Switching Regulator Series
Output 1.5A or Less High-efficiency Step-down Switching Regulator with Built-in Power MOSFET
BD9161FVM
No.09027EAT29
Description ROHM's high efficiency step-down switching regulator BD9161FVM is a power supply designed to produce 1.2volts (low voltage) from 3.3volts power supply line. Offers high efficiency with our original pulse skip control technology and synchronous rectifier. Employs a current mode control system to provide faster transient response to sudden change in load. Features 1) Offers fast transient response with current mode PWM control system. 2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Pch FET) 3) Incorporates 100% Duty function. 4) Incorporates soft-start function. 5) Incorporates thermal protection and ULVO functions. 6) Incorporates short-current protection circuit with time delay function. 7) Incorporates shutdown function Icc=0A (Typ.) 8) Employs small surface mount package MSOP8 Use Power supply for HDD, DVS and for LSI of CPU, ASIC Absolute Maximum Rating (Ta=25) Parameter VCC voltage PVCC voltage EN Voltage SW, ITH Voltage Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Power Dissipation 4 EN voltage
Symbol VCC PVCC EN SW,ITH Pd1 Pd2 Topr Tstg Tjmax
Rating -0.3+7 *1 -0.3+7
*1
Unit V V V V mW mW
-0.3+7 -0.3+7 387.5*2 587.4*3 -25+85 -55+150 +150
*1 Pd should not be exceeded. *2 Derating in done 3.1mW/ for temperatures above Ta=25. *3 Derating in done 4.7mW/ for temperatures above Ta=25,Mounted on 70mmx70mmx1.6mm Glass Epoxy PCB.
Operating Conditions (Ta=25) Parameter VCC voltage PVCC voltage EN voltage Output Voltage Setting Range SW, ITH average output current
*4 Pd should not be exceeded.
Symbol VCC*4 PVCC*4 EN SW,ITH Isw*4
Limits Min. 2.5 2.5 0 1.0 Typ. 3.3 3.3 Max. 4.5 4.5 VCC 3.3 0.6
Unit V V V V A
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1/13
2009.05 - Rev.A
BD9161FVM
Electrical Characteristics (Ta=25, VCC=PVCC=3.3V, EN=VCC, unless otherwise specified.) Limits Parameter Symbol Min. Typ. Standby current ISTB 0 Bias current ICC 200 EN Low voltage VENL GND EN High voltage VENH 2.0 VCC EN input current IEN 1 Oscillation frequency FOSC 0.8 1 Pch FET ON resistance RONP 0.35 Nch FET ON resistance RONN 0.37 Output voltage VOUT 0.784 0.8 ITH SInk current ITHSI 10 20 ITH Source Current ITHSO 10 20 UVLO threshold voltage VUVLO1 2.2 2.3 UVLO hysteresis voltage VUVLO2 2.22 2.35 Soft start time TSS 0.5 1 Timer latch time TLATCH 1 2 Output Short circuit Threshold Voltage VSCP 0.4
Technical Note
Max. 10 400 0.8 10 1.2 0.6 0.68 0.816 2.4 2.5 2 3 0.56
Unit A A V V A MHz V A A V V ms ms V
Conditions EN=GND Standby mode Active mode VEN=3.3V PVCC=3.3V PVCC=3.3V VOUT =H VOUT =L VCC=HL VCC=LH SCP/TSD operated VOUT =HL
Block Diagram, Application Circuit
EN 3
VCC
2.90.1
Max3.25(include.BURR)
0.290.15 0.60.2
4
+6 -4
VREF Current Comp. RQ Gm Amp. S SLOPE VCC Soft Start OSC CLK Current Sense/ Protect + Driver Logic
8 7
VCC 3.3V Input
8
5
4.00.2
2.80.1
PVCC
D91 6 1
Lot No.
1
4
0.475
0.9Max. 0.750.05 0.080.05
1PIN MARK
0.145 -0.03
+0.05
6 SW PGND 5 4 GND
Output
S
+0.05 0.22 -0.04
UVLO TSD SCP
0.65
0.08 S
1 ADJ 2
ITH
MSOP8 (Unit:mm)
Fig.1 BD9161FVM Dimension Pin No. & function table Pin No. 1 2 3 4 5 6 7 8
Fig.2 BD9161FVM Block Diagram PIN function Output voltage Feedback pin (Adjustable) GmAmp output pin/Connected phase compensation capacitor Enable pin (Active High) Ground Nch FET source pin Pch/Nch FET drain output pin Pch FET source pin VCC power supply input pin
Pin name ADJ ITH EN GND PGND SW PVCC VCC
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1/13
2009.05 - Rev.A
BD9161FVM
Characteristics data(Reference data)
3.0
Technical Note
3.0
3.0
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
VOUT=2.5V Ta=25 Io=0A
2.0
VOUT=2.5V
VOUT=2.5V
2.0
2.0
1.0
1.0
1.0
VCC=3.3V Ta=25 Io=0A
0.0 0 1 2 3 EN VOLTAGE:VEN[V] 4
VCC=3.3V Ta=25
0.0 0 1 2 OUTPUT CURRENT:IOUT [A] 3
0.0 0 1 2 3 INPUT VOLTAGE:VCC[V] 4
Fig.3 Vcc-Vout
Fig.4 Ven-Vout
Fig.5 Iout-Vout
2.55 2.54
OUTPUT VOLTAGE:VOUT[V]
100
FREQUENCY:FOSC[MHz]
2.53 2.52 2.51 2.50 2.49 2.48 2.47 2.46 2.45
EFFICIENCY:[%]
VOUT=2.5V VCC=3.3V Io=0A
90 80 70 60 50 40 30 20 10 0
1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00
1 10 100 OUTPUT CURRENT:IOUT[mA] 1000
VCC=3.3V VCC=3.3V
VOUT=2.5V VCC=3.3V Ta=25
-25 -15
-5
5
15
25
35
45
55
65
75
85
-25 -15
-5
5
15
25 35
45
55
65
75
85
TEMPERATURE:Ta[]
TEMPERATURE:Ta[]
Fig. 6 Ta-VOUT
Fig.7 Efficiency
Fig.8 Ta - Fosc
0.40 0.35
ON[]
2.0 1.8
1.2
VCC=3.3V
FREQUENCY:FOSC[MHz]
15 25 35 45 55 65 75 85
0.30 0.25 0.20 0.15 0.10 0.05 0.00
ON RESISTANCE:R
EN VOLTAGE:VEN[V]
VCC=3.3V PMOS NMOS
1.6 1.4 1.2 1.0 0.8 0.6 0.4
VCC=3.3V
1.1
1
0.9
VCC=3.3V
-25 -15 -5 5 15 25 35 45 55 65 75 85
0.2 0.0
-25 -15 -5 5
TEMPERATURE:Ta[]
TEMPERATURE:Ta[]
0.8 2.5
3 3.5 4 INPUT VOLTAGE:VCC[V]
4.5
Fig.9 Ta-VEN
Fig.10 Ta-ICC
Fig.11 Vcc-Fosc
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2/13
2009.05 - Rev.A
BD9161FVM
Characteristics data(Reference data) - Continued
Technical Note
VCC=PVCC =EN
VOUT=2.5V
SLLMTM control
VOUT=2.5V
PWM control
VOUT=2.5V
SW
SW
VOUT VCC=3.3V Ta=25 Io=0A
VOUT VCC=3.3V Ta=25
VOUT VCC=3.3V Ta=25
Fig.12 Soft start waveform
Fig.13 SW waveform Io=10mA
Fig.14 SW waveform Io=500mA
100% Duty
VOUT=2.5V VOUT
VOUT=2.5V VOUT
VOUT=2.5V
SW
VOUT VCC=2.7V Ta=25
IOUT
IOUT VCC=3.3V Ta=25 VCC=3.3V Ta=25
Fig. 15 SW waveform Io=600mA
Fig. 16 Transient response Io=250500mA(10s)
Fig.17 Transient response Io=500250mA(10s)
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3/13
2009.05 - Rev.A
BD9161FVM
Technical Note
Information on advantages Advantage 1Offers fast transient response with current mode control system. Conventional product (VOUT of which is 2.5 volts) BD9161FVM (Load response IO=250mA500mA)
VOUT VOUT 98mV 40mV
IOUT
IOUT
Voltage drop due to sudden change in load was reduced by about 50%. Fig.18 Comparison of transient response Advantage 2 Offers high efficiency for all load range. For lighter load: TM Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
Efficiency [%]
100
For heavier load: Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor. ON resistance of P-channel MOS FET: 0.35 (Typ.) ON resistance of N-channel MOS FET: 0.37 (Typ.)
SLLMTM
50
PWM
TM
inprovement by SLLM
system
improvement by synchronous rectifier
0 0.001
0.01 0.1 Output current Io[A]
1
Fig.19 Efficiency
Achieves efficiency improvement for heavier load. Offers high efficiency for all load range with the improvements mentioned above. Advantage 3 Supplied in smaller package due to small-sized power MOS FET incorporated. Allows reduction in size of application products Output capacitor Co required for current mode control: 10 F ceramic capacitor Inductance L required for the operating frequency of 1 MHz: 4.7 H inductor Reduces a mounting area required.
VCC 15mm Cin CIN DC/DC Convertor Controller RITH L VOUT Co 10mm CITH CO L
RITH CITH
Fig.20 Example application
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4/13
2009.05 - Rev.A
BD9161FVM
Technical Note
Operation BD9161FVM is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for TM heavier load, while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency. Current mode PWM control Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback. PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control repeats this operation.
TM SLLM (Simple Light Load Mode) control When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa. Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching dissipation and improves the efficiency.
100% Duty control Max duty is 100%. (@ Pch MOS FET always ON) In usual PWM control, in case output voltage cannot keep (ex, drop of input voltage), oscillation frequency becomes lower and finally it becomes 100% duty. The output voltage is a value that depends only by on a voltage hang from the input voltage to Pch MOS FET, and can keep the output voltage even with the low input voltage.
SENSE Current Comp Level Shift Gm Amp. ITH OSC FB RESET SET RQ S Driver Logic SW Load IL VOUT
VOUT
Fig.21 Diagram of current mode PWM control
Current Comp SET PVCC SENSE FB GND GND GND IL(AVE) SET Current Comp PVCC SENSE FB GND GND
RESET SW IL
RESET SW
GND IL 0A
VOUT
VOUT(AVE)
VOUT
VOUT(AVE)
Not switching
Fig.22 PWM switching timing chart
Fig.23 SLLM
TM
switching timing chart
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5/13
2009.05 - Rev.A
BD9161FVM
Technical Note
Description of operations Soft-start function EN terminal shifted to "High" activates a soft-starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. Shutdown function With EN terminal shifted to "Low", the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0F (Typ.). UVLO function Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of 50 mV (Typ.) is provided to prevent output chattering.
Hysteresis 50mV
VCC
EN
VOUT
Tss Soft start Standby mode Operating mode Standby mode UVLO
Tss
Tss
Operating mode
Standby mode EN
Operating mode
Standby mode
UVLO
UVLO
Fig.24 Soft start, Shutdown, UVLO timing chart
Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the fixed time (TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO.
EN
Output OFF latch VOUT Limit IL 1msec Standby mode EN Standby mode Timer latch EN
Operating mode
Operating mode
Fig.25 Short-current protection circuit with time delay timing chart
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6/13
2009.05 - Rev.A
BD9161FVM
Technical Note
Switching regulator efficiency Efficiency may be expressed by the equation shown below: POUT x100[%]= POUT = VOUTxIOUT x100[%]= x100[%] VinxIin Pin POUT+PD Efficiency may be improved by reducing the switching regulator power dissipation factors PD as follows: Dissipation factors: 2 1) ON resistance dissipation of inductor and FETPD(I R) 2) Gate charge/discharge dissipationPD(Gate) 3) Switching dissipationPD(SW) 4) ESR dissipation of capacitorPD(ESR) 5) Operating current dissipation of ICPD(IC) 1)PD(I R)=IOUT x(RCOIL+RON) (RCOIL[]DC resistance of inductor, RON[]ON resistance of FET IOUT[A]Output current.) 2)PD(Gate)=CgsxfxV (Cgs[F]Gate capacitance of FET, f[H]Switching frequency, V[V]Gate driving voltage of FET) 2 Vin xCRSSxIOUTxf 3)PD(SW)= (CRSS[F]Reverse transfer capacitance of FET, IDRIVE[A]Peak current of gate.) IDRIVE 2 4)PD(ESR)=IRMS xESR (IRMS[A]Ripple current of capacitor, ESR[]Equivalent series resistance.) 5)PD(IC)=VinxICC (ICC[A]Circuit current.) Consideration on permissible dissipation and heat generation As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation.
1000 Power dissipation:Pd [mW]
2 2
800 587.4mW
Using an IC alone j-a=322.6/W mounted on glass epoxy PCB j-a=212.8/W
P=IOUT2x(RON) RON=DxRONP+(1-D)xRONN DON duty (=VOUT/VCC) RONPON resistance of P-channel MOS FET RONNON resistance of N-channel MOS FET IOUTOutput current
600
400
387.5mW
200
0 0 25 50 75 85 100 125 150 Ambient temperature:Ta []
Fig.26 Thermal derating curve (MSOP8) If VCC=3.3V, VOUT=2.5V RONP=0.35, RONN=0.37 IOUT=0.6A, for example, D=VOUT/VCC=2.5/3.3=0.758 RON=0.758x0.35+(1-0.758)x0.37 =0.2653+0.08954 =0.35484[] P=0.6 x0.35484 127.7[mV] As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
2
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7/13
2009.05 - Rev.A
BD9161FVM
Selection of components externally connected 1. Selection of inductor (L)
IL IL VCC
Technical Note
The inductance significantly depends on output ripple current. As seen in the equation (1), the ripple current decreases as the inductor and/or switching frequency increases. [A](1) LxVCCxf Appropriate ripple current at output should be 2030% more or less of the maximum output current. IL=0.25xIOUTmax. [A](2) IL= L= (VCC-VOUT)xVOUT ILxVCCxf [H](3) (VCC-VOUT)xVOUT
IL VOUT L Co
Fig.27 Output ripple current
(IL: Output ripple current, and f: Switching frequency)
* Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. If VCC=3.3V, VOUT=2.5V, f=1MHz, IL=0.25x0.6A=0.15A (3.3-2.5)x2.5 L 0.15x3.3x1M 4.04 * Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency. 2. Selection of output capacitor (CO)
VCC
Output capacitor should be selected with the consideration on the stability region and the equivalent series resistance required to smooth ripple voltage. Output ripple voltage is determined by the equation (4)
VOUT
L
ESR Co
VOUT=ILxESR [V](4) (IL: Output ripple current, ESR: Equivalent series resistance of output capacitor) *Rating of the capacitor should be determined allowing sufficient margin against output voltage. Less ESR allows reduction in output ripple voltage.
Fig.28 Output capacitor Inappropriate capacitance may cause problem in startup. A 10F to 100F ceramic capacitor is recommended.
3. Selection of input capacitor (Cin)
VCC
Cin
Input capacitor to select must be a low ESR capacitor of the capacitance sufficient to cope with high ripple current to prevent high transient voltage. The ripple current IRMS is given by the equation (5):
VOUT
L
Co
VCC < Worst case > IRMS(max.) When VCC is twice the Vout, IRMS=
IRMS=IOUTx
VOUT(VCC-VOUT)
[A](5) IOUT 2
If VCC=3.3V, VOUT=2.5V, and IOUTmax.=0.6A 2.5(3.3-2.5) IRMS=0.6x =0.284[ARMS] 5 A low ESR 10F/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
Fig.29 Input capacitor
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8/13
2009.05 - Rev.A
BD9161FVM
Technical Note
4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.) A Gain [dB] fp(Max.) 0 IOUTMin. 0 IOUTMax. fz(ESR)
1 2xROxCO 1 fz(ESR)= 2xESRxCO fp= Pole at power amplifier When the output current decreases, the load resistance Ro increases and the pole frequency lowers. fp(Min.)= 1 2xROMax.xCO 1 2xROMin.xCO [Hz]with lighter load [Hz]with heavier load
Phase [deg]
-90
Fig.30 Open loop gain characteristics fp(Max.)=
A Gain [dB] 0 0 fz(Amp.)
Zero at power amplifier Increasing capacitance of the output capacitor lowers the pole frequency while the zero frequency does not change. (This is because when the capacitance is doubled, the capacitor ESR reduces to half.) fz(Amp.)= 1 2xRITH.xCITH
Phase [deg]
-90
Fig.31 Error amp phase compensation characteristics
VCC
Cin EN VOUT VOUT ITH RITH CITH
VCC,PVCC
L SW ESR RO VOUT
GND,PGND
CO
Fig.32 Typical application Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. fz(Amp.)= fp(Min.) 1 2xRITHxCITH = 1 2xROMax.xCO
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9/13
2009.05 - Rev.A
BD9161FVM
5. Determination of output voltage The output voltage VOUT is determined by the equation (6): VOUT=(R2/R1+1)xVADJ(6) VADJ: Voltage at ADJ terminal (0.8V Typ.) With R1 and R2 adjusted, the output voltage may be determined as required. (Adjustable output voltage range 1.0V3.3V ) Use 1 k100 k resistor for R1. If a resistor of the resistance higher than 100 k is used, check the assembled set carefully for ripple voltage etc.
Technical Note
L 6 SW 1 ADJ R1 Co R2 Output
Fig.33 Determination of output voltage BD9161FVM Cautions on PC Board layout
1 2 RITH EN CITH 4 3
ADJ ITH EN GND
VCC PVCC SW PGND
8 RIN 7 CIN 6 5 CO L VOUT GND VCC
Fig.34 Board layout

For the sections drawn with heavy line, use thick conductor pattern as short as possible. Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND. Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
Recommended component lists with above applications Symbol Part Value L RIN CIN CO Coil Resistance Ceramic capacitor Ceramic capacitor Ceramic capacitor 4.7H 10 10F 10F VOUT=1.0V VOUT=1.2V VOUT=1.5V VOUT=1.8V VOUT=2.5V VOUT=1.0V VOUT=1.2V VOUT=1.5V VOUT=1.8V VOUT=2.5V
CITH
RITH
Resistance
820pF 560pF 470pF 470pF 330pF 6.8k 8.2k 12k 12k 15k
Manufacturer TDK Sumida ROHM Kyocera Kyocera murata murata murata murata murata ROHM ROHM ROHM ROHM ROHM
Series VLF5014AT-4R7M1R1 CMD6D11B MCR03 Series CM316X5R106K10A CM316X5R106K10A GRM18 Series GRM18 Series GRM18 Series GRM18 Series GRM18 Series MCR03 Series MCR03 Series MCR03 Series MCR03 Series MCR03 Series
* The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode established between the SW and PGND pins.
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10/13
2009.05 - Rev.A
BD9161FVM
I/O equivalence circuit
PVCC PVCC PVCC
Technical Note
EN pin
10k EN
SW pin
SW
ADJ pin
10k ADJ
ITH pin
VCC
ITH
Fig.36 I/O equivalence circuit
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11/13
2009.05 - Rev.A
BD9161FVM
Technical Note
Cautions on use 1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4.Operation in Strong electromagnetic field Be noted that using the IC in the strong electromagnetic radiation can cause operation failures. 5. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 6. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. 7. Input to IC terminals + This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed. If a resistor is joined to a transistor terminal as shown in Fig 37: P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements.
Resistor Pin A Pin A
P
+
Transistor (NPN) Pin B
C B E B P P
+
Pin B
N P P
+
N
N
Parasitic element
N
P+
N N
C E
P substrate Parasitic element
GND
P substrate Parasitic element
GND GND GND
Parasitic element
Other adjacent elements
Fig.37 Simplified structure of monorisic IC 8. Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
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12/13
2009.05 - Rev.A
BD9161FVM
Ordering part number
Technical Note
B
D
9
Part No.
1
6
1
F
V
M
-
T
R
Part No.
Package FVM:MSOP8
Packaging and forming specification TR: Embossed tape and reel (MSOP8)
MSOP8

2.90.1 (MAX 3.25 include BURR)
8765
Tape
0.290.15 0.60.2
+6 4 -4
Embossed carrier tape 3000pcs TR
The direction is the 1pin of product is at the upper right when you hold
Quantity Direction of feed
4.00.2
2.80.1
( reel on the left hand and you pull out the tape on the right hand
1pin
)
1 234
1PIN MARK 0.475 S +0.05 0.22 -0.04 0.08 S 0.65
+0.05 0.145 -0.03
0.9MAX 0.750.05
0.080.05
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
13/13
2009.05 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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